发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the area and the test time of a semiconductor integrated circuit which mounts a PLL circuit having a current charge pump with a current source supplied from a feedback loop of a base voltage generator circuit. SOLUTION: In a standby for the actual operation, a base clock signal, a feedback clock and a reference clock are alternately inputted to a phase comparator to monitor a lop filter output signal. The current of the output signal is monitored to detect failures of a base voltage generator circuit, a current charge pump and the phase comparator at the same time.
申请公布号 JP2002344309(A) 申请公布日期 2002.11.29
申请号 JP20010144401 申请日期 2001.05.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SUMIDA MASAYA
分类号 H03L7/08 主分类号 H03L7/08
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