发明名称 DIGITAL INTEGRATION DEVICE
摘要 PROBLEM TO BE SOLVED: To maintain the arithmetic accuracy and to reduce the circuit scale of a digital integration device performing the cumulative processing of multiplied results with a multiplicand and a multiplier as a mantissa part and an exponent part. SOLUTION: The digital integration device is provided with a memory 5 storing cumulative added results, a size judgment part 6 judging the size relation of an inputted exponent part (weighting coefficient) and the exponent part read from the memory 5, selectively outputting the larger exponent part and writing it in the memory 5, a first bit operation part 1 adding a virtual bit to an inputted mantissa part (input data) and performing a shift processing by shift control information from the size judgment part 6, a second bit operation part 2 inputting the mantissa part of the cumulative added results until a previous time read from the memory 5 and performing the shift processing by the shift control information from the size judgment part 6 and an adder 3 adding the mantissa parts from the first and second bit operation parts 1 and 2 and turning them to the mantissa part to be written to the memory 5.
申请公布号 JP2002342070(A) 申请公布日期 2002.11.29
申请号 JP20010149805 申请日期 2001.05.18
申请人 FUJITSU LTD 发明人 SATO HIDEKAZU;INOUE TAKESHI;SUNAGA SUMIMASA;SHIMIZU MASAHIKO;MATSUYAMA KOJI
分类号 G06F7/53;G06F7/00;G06F7/52;G06F7/523 主分类号 G06F7/53
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