| 摘要 |
PROBLEM TO BE SOLVED: To obtain desired data at an early stage by fetching write data in a writeback operation and also to reduce traffic of a local bus by canceling access to a main memory in the case an access address to the main memory in the writeback operation coincides with an address subjected to read access by a host bridge in a configuration in which a processor having a writeback type cache and the host bridge share the main memory through the local bus. SOLUTION: This host bridge 200 is provided with: an address hit decision circuit 220 for detecting that the read access address to the main memory 300 held in an address holding circuit 210 coincides with a line address writeback operation by the processor 100; and a memory access control circuit 230 for fetching the write data in the writeback operation and canceling the access to the main memory 300 in the case a hit decision is made.
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