发明名称 DEMODULATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a demoduration circuit which is less affected by variation in the properties of elements and reduced in circuit scale. SOLUTION: Input signals are converted into digital signals by an A/D converting means 1, and the converted digital signals held by a one time-slot holding means 2 for a one time slot period and signals obtained by delaying the signals outputted from the means 2 by a one time slot period by the use of a one time-slot delaying means 3 are phase-detected by a first phase detection means 4, and the phase-detection result is demodulated into 1 and 0 through a first discrimination reproduction means to fetch out signals of a channel 1.0r, the converted digital signals held by a one time-slot holding means 2 for a one time slot period and signals which are obtained by delaying the signals outputted from the means 2 by a one time slot period by the use of the one time-slot delaying means 3 and furthermore phase-shifted by a π/2 phase shifting means 5 are phase-detected by a second phase detection means 6, and the phase- detection result is demodulated into 1 and 0 through a second discrimination reproduction means to fetch out signals of a channel 2.
申请公布号 JP2002344551(A) 申请公布日期 2002.11.29
申请号 JP20010142729 申请日期 2001.05.14
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TERADA JUN;MATSUTANI YASUYUKI
分类号 H04L27/227;H04L27/22 主分类号 H04L27/227
代理机构 代理人
主权项
地址