| 摘要 |
PROBLEM TO BE SOLVED: To obtain a Viterbi decoder in which the circuitry is simplified as compared with a conventional one while reducing power consumption and the circuit area. SOLUTION: A path select signal memory section 10 outputs each decoding data B'S<i> k corresponding to a branch of a specified time past from path select signals SEL0 and SEL1 in the surviving path leading to each state at current time. Shift registers 11 and 12 store the path select signals SEL0 and SEL1 in the order of time. A binary output unit 18 outputs a decoding bit corresponding to a branch of a specified time past in the surviving path. Output signal line and selector arrays 13 and 14 of the binary output unit 18 are connected similarly to a Trellis diagram corresponding to encoding.
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