DIGITAL SIGNAL COMPRESSION CIRCUIT AND DIGITAL SIGNAL DECOMPRESSION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a digital signal compression circuit and a digital signal decompression circuit characterized in small power consumption. SOLUTION: The digital signal compression circuit comprises a circuit where a discrete cosine converter comprising registers 3, 3a-3p, a bit slice distributor 4, a shifter 5, a read only memory 6, and an adder 7 is connected with a branch division circuit 1 and a selector 2. The branch division circuit 1 makes a decision whether eight continuous input data are all 0 or not and delivers a discrimination signal indicating the decision results to the selector 2. The selector 2 delivers 0 directly as the output data from the discrete cosine converter if eight input data are all 0, otherwise delivers data from a shift register comprising the registers 3i-3p as the output data from the discrete cosine converter.