发明名称 SYSTEM FOR GENERATING PSEUDO FAULT
摘要 PROBLEM TO BE SOLVED: To enable fault processing function verification of a system program about a processor that does not have a mechanism for simulatedly generating a fault condition in each fault that can be detected by the processor with operation of a hardware logical circuit for fault detection and a fault which can not be directly generated by a pseudo fault injection mechanism with operation of the hardware logical circuit for fault detection such as a case in which a pseudo fault necessary for a fault test can be generated only by designating the address of a storage device when an area is arranged on a storage area only for hardware in each different function and a storage device fault in the area is reported as a function fault of a processor. SOLUTION: The pseudo fault injection mechanism to the storage device mounted on a hardware is used, a pseudo storage mechanism fault is generated in a data storage area for control corresponding to each fault of the processor, and various faults are generated.
申请公布号 JP2002342116(A) 申请公布日期 2002.11.29
申请号 JP20010145778 申请日期 2001.05.16
申请人 HITACHI LTD 发明人 KOYAMA TOSHIHIRO
分类号 G06F12/16;G06F11/22;G06F11/28 主分类号 G06F12/16
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