发明名称 VERTICAL FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
摘要 A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) are formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of a of recesses (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).
申请公布号 US2002175365(A1) 申请公布日期 2002.11.28
申请号 US19990447298 申请日期 1999.11.23
申请人 HIRAYAMA TERUO 发明人 HIRAYAMA TERUO
分类号 H01L21/336;H01L21/8234;H01L21/8247;H01L27/115;H01L29/78;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 主分类号 H01L21/336
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