Data remanence safeguarding method for microprocessor system uses control device detecting high and low levels for coupling random-access memories with high and low access rates

摘要

The data remanence safeguarding method has a control device (S) coupling random-access memory regions (DRAM1,.The control device detects a low level for initiating data transfer with switching to external or internal buffering for the random-access memory with the lower access rate and detects a high level for initiating data transfer from the random-access memory with the lower access rate to the random access memory with the higher access rate. An Independent claim for a data remanence safeguarding device for a microprocessor system is also included.