发明名称 Adjustable I/O timing from externally applied voltage
摘要 An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.
申请公布号 US2002178322(A1) 申请公布日期 2002.11.28
申请号 US20020196314 申请日期 2002.07.16
申请人 MICRON TECHNOLOGY, INC. 发明人 GANS DEAN;STAVE ERIC J.;PAWLOWSKI JOSEPH THOMAS
分类号 G06F13/42;(IPC1-7):G06F12/00 主分类号 G06F13/42
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