发明名称 |
A method for simulation of circuit units, such as microprocessors and graphics cards, being verified, involves using test benches/models or circuit simulation models |
摘要 |
A method for simulating a circuit unit (101) by an arrangement with self-registering test bench elements (102a..102n) connecting the circuit unit to the simulation arrangement. Method involves connecting the circuit unit being verified via at least one self-registering test bench element, and supplying a control data flow (111) from the test bench controller (103) to the circuit unit being verified, via a test bench element, and then delivering a test bench element data flow from the test bench element to an associated self-registering element (105,106) of the simulation arrangement and then supplying a self-registering data flow to the test bench controller (103) of the simulation arrangement, and driving the test bench element by the test-bench controller (103) with the control data flow (111). An Independent claim is given for a device for self-registering of test bench elements.
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申请公布号 |
DE10124175(A1) |
申请公布日期 |
2002.11.28 |
申请号 |
DE20011024175 |
申请日期 |
2001.05.17 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HENFTLING, RENATE;ECKER, WOLFGANG;ZINN, ANDREAS;BAUER, MATTHIAS |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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