发明名称 |
HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN |
摘要 |
Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications. |
申请公布号 |
WO02095586(A2) |
申请公布日期 |
2002.11.28 |
申请号 |
WO2002GB02302 |
申请日期 |
2002.05.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED |
发明人 |
CHEN, HOWARD, HAO;HSU, LOUIS, LU-CHEN;WANG, LI-KONG |
分类号 |
G01R31/28;G06F11/22;G06F11/27;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|