发明名称 |
Efficient parallel testing of semiconductor devices using a known good device to generate expected responses |
摘要 |
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
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申请公布号 |
US2002175697(A1) |
申请公布日期 |
2002.11.28 |
申请号 |
US20020208173 |
申请日期 |
2002.07.29 |
申请人 |
FORMFACTOR, INC. |
发明人 |
MILLER CHARLES A.;ROY RICHARD S. |
分类号 |
G01R31/319;G01R31/3193;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/319 |
代理机构 |
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地址 |
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