METHOD FOR GENERATING INPUT/OUTPUT CONTROL CLOCK CAPABLE OF ASSURING TIMING MARGIN AND REDUCING POWER NOISE AND POWER CONSUMPTION AND SEMICONDUCTOR MEMORY DEVICE REALIZED ACCORDING THERETO

摘要

PURPOSE: A method for generating an input/output control clock is provided which can assure a timing margin and can reduce a power noise and power consumption. CONSTITUTION: According to a semiconductor memory device realized according to the method, an input control clock(SCLKD) used in a data input/output circuit(61) and an input control clock(SCLKP) used in a pipeline circuit(63) are generated by an additional clock buffer. That is, the first clock buffer(65) buffers the first clock(ESCLK) and then provides the buffered clock to the pipeline circuit as the input control clock(SCLKP), and the second clock buffer(67) buffers an output signal of the clock buffer and then provides the buffered clock to the data input/output circuit as the input control clock(SCLKD).