发明名称 BLOCK CIRCUIT FOR CALCULATION AND VERIFYING CRC-32 HAVING VARIABLE LENGTH USING INPUT PARAMETER
摘要 PURPOSE: A block circuit for calculating and verifying the CRC(Cyclic Redundency Check)-32 having a variable length using an input parameter is provided to perform the calculation and the verification of the CRC-32 with a single clock cycle for the input bit number fit to a changed interface size even if carries out the data transaction with any external interface. CONSTITUTION: A CRC-32 C/L part calculates and verifies the CRC-32 by receiving the input of the external variable data. An input selection part(11) selects the input from an initial value and the input from the CRC-32 C/L part by receiving a necessary control signal. A CRC-32 REG part is a register temporally storing a CRC-32 calculation result. An inverter part(13) inverts a final CRC-32 syndrome in order to support a recommendation of the ITU-T(International Telecommunications Union - Telecommunication Standardization Sector) 1.363. A CRC-32 result selection part(14) selects a final calculation result or an inverted result of the CRC-32 calculation. A prediction part(15) stores the prediction value of the syndrome generated by completing a CRC-32 verification logic. A CRC-32 comparison part distinguishes between the true or the false of a CRC-32 verification result.
申请公布号 KR20020087823(A) 申请公布日期 2002.11.23
申请号 KR20010028186 申请日期 2001.05.16
申请人 SONH, SEUNG IL 发明人 SONH, SEUNG IL
分类号 G06F11/14;(IPC1-7):G06F11/14 主分类号 G06F11/14
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