发明名称 FIFO MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce scale of circuit by constituting a FIFO memory device using scan chain in a function block being not yet used by utilizing effectively a function block not to be used. SOLUTION: In a semiconductor integrated circuit designed so as to test easily using scan FF, the device is provided with a selector in which scan chain of a circuit block being not functioned during operation using a FIFO memory device is used as a memory section of the FIFO memory device and a scan input and a FIFO input are selected, and a multiplexer selecting data initially selected and outputted it. Thereby, as the FIFO memory device is not required to provided exclusively, the scale of circuit can be reduced.
申请公布号 JP2002334572(A) 申请公布日期 2002.11.22
申请号 JP20010133736 申请日期 2001.05.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAGISHI SHIRO
分类号 G01R31/28;G06F11/22;G06F12/00;G11C7/00;G11C29/00;G11C29/22 主分类号 G01R31/28
代理机构 代理人
主权项
地址