发明名称 METHOD FOR SIMULATING POWER CONSUMPTION OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for estimating power consumption of a semiconductor integrated circuit of a processor on which an MMU(memory managing unit) and a cache memory are mounted and to convert a logical address into a physical address at an architecture level at high speed in the processor. SOLUTION: This method is preliminarily provided with pieces of power consumption information by every MMU operation of an MMU part 1302, write-back and right-through modes are distinguished, power consumption information by every cache operation including start of write of dirty data is provided, power consumption information of a CPU part 1301 by every instruction for a cache part 1303. Power to be consumed in the entire object circuit of simulation is calculated from the pieces of power consumption information during execution or after completion of simulation.
申请公布号 JP2002334128(A) 申请公布日期 2002.11.22
申请号 JP20010140462 申请日期 2001.05.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 BABA TAKAHIDE
分类号 G06F12/08;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F12/08
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