SYNCHRONOUS DRAM(SDRAM) HAVING DATA LATCH CIRCUIT OUTPUTTING DATA INPUTTED BY BEING SYNCHRONIZED TO PLURAL CONTROL SIGNALS

摘要

PURPOSE: A synchronous DRAM(SDRAM) having a data latch circuit outputting data inputted by being synchronized to plural control signals is provided, which can reduce an effective data window and can minimize a chip area. CONSTITUTION: According to the synchronous DRAM(SDRAM), the first buffer(421) generates the first internal control signal(DQS_internal) by buffering an external control signal(DQS). The second buffer(431) generates the second internal control signal(DS) by buffering the external control signal, and the third buffer(441) generates an internal clock signal(PCLK) by buffering an external clock signal(CLK). And a data latch circuit(411) receives data from the external, and outputs the received data by being synchronized to the first and the second internal control signal and the internal clock signal in sequence.