发明名称 SIGNAL GENERATOR CIRCUIT, TIMING RECOVERY PLL, SIGNAL GENERATION SYSTEM AND SIGNAL GENERATING METHOD
摘要 PROBLEM TO BE SOLVED: To quickly read signals from recording medium by eliminating the need for a means of locking with initial frequency, to thereby eliminate the lock-up time. SOLUTION: A control signal, for controlling a controlled oscillator of a signal generator circuit for generating a write clock, is fed as a reference signal to a signal generator circuit for generating a read clock. The read clock generator circuit has no need of generating reference signals in own circuit but can feed the fed reference signal added with a timing error, when reading signals, to the controlled oscillator. This eliminates both the means for locking the read clock with an initial frequency and the time (lock up time) taken for locking the read clock at the initial frequency, resulting in the circuit scale and the signal read time being reduced.
申请公布号 JP2002335155(A) 申请公布日期 2002.11.22
申请号 JP20010141713 申请日期 2001.05.11
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 MATSUNAMI HIROYUKI;OKADA KOJI
分类号 G11B20/14;H03L7/07;H03L7/08;H03L7/089;H03L7/091;H03L7/093;H03L7/099;H03L7/18 主分类号 G11B20/14
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