发明名称 DISPLAY DEVICE OF ERROR RATE
摘要 <p>PROBLEM TO BE SOLVED: To provide a display device of an error rate which prevents the display of an erroneous error rate. SOLUTION: A transmitted signal is decoded as an output in Viterbi decoding by a Viterbi decoder 1. When conducting Viterbi decoding, the Viterbi decoder 1 inputs an error flag into a Viterbi error rate processing circuit 4. The transmitted signal deinterleaved by a bite de-interleaving circuit 2 is decoded in Reed- Solomon code by a Reed-Solomon decoder 3. The Reed-Solomon decoder 3 inputs an error flag into an error rate display circuit 7. The error flag from the Viterbi decoder 1 is input into a Viterbi error rate processing circuit 4 to calculate a first error rate. A Reed-Solomon error rate processing circuit 6 retrieves the error flag from the Reed-Solomon decoder 3, to calculate a second error rate. A Viterbi decode control signal, a 47h detection signal, the first error rate, the second error rate, and a correction disability flag are input into an error rate display circuit 7 and displaying is made.</p>
申请公布号 JP2002335163(A) 申请公布日期 2002.11.22
申请号 JP20010138653 申请日期 2001.05.09
申请人 NEC CORP 发明人 WATANABE SHINJI
分类号 G06F11/08;G06F11/10;G06F11/32;H03M13/01;H03M13/41;H04L1/00;H04N7/24;H04N19/00;H04N19/102;H04N19/134;H04N19/166;H04N19/196;H04N19/44;H04N19/65;H04N19/89;(IPC1-7):H03M13/01 主分类号 G06F11/08
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