Address control apparatus of semiconductor memory device using bank address

摘要

An address control apparatus for a semiconductor memory device using a bank address, and more particularly an address control apparatus for a semiconductor memory device using a bank address being concurrently used as a row address in accordance with an architectural bank in realizing various dynamic random access memory (DRAM) macro sets more than 2M~64M, utilizing a memory compiler in embedded-DRAM, resulting in reduced design time for the macro sets with a minimum of circuit elements.