发明名称 ARCHITEKTUR FÜR TEILBARE WARTESCHLANGEN UND WARTESCHLANGENVERFAHREN
摘要 A split-queue architecture and method of queuing entries to the queue has a three part queue. The first part of the queue is a write side in which entries to the queue are received. The second part of the queue is a read side from which entries exit the queue after flowing through the queue. Entries normally flow from the write side to the read side. An overflow area, located off-chip in an external memory, forms part of the queue on an as needed basis to store entries from the write side when the read side no longer has capacity to accept more entries from the write side. When the read side regains capacity to accept more entries, the overflow area transfers its entries to the read side.
申请公布号 DE69808732(D1) 申请公布日期 2002.11.21
申请号 DE1998608732 申请日期 1998.01.30
申请人 ADVANCED MICRO DEVICES, INC. 发明人 RUNALDUE, JEFFERSON
分类号 H04L13/08;G06F5/06;H04L12/18;H04L12/24;H04L12/56;H04Q3/545;(IPC1-7):H04L12/44;H04L29/06 主分类号 H04L13/08
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