| 摘要 |
<p>A semiconductor chip (102) includes a plurality of regional clock distribution nodes (106) located on the semiconductor chip (102); a plurality of clock buffers (L), each including a delay lock loop (DLL) circuit providing a DDL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of an Nth level subset of the plurality of clock buffers (L) being coupled to respective ones of the plurality of regional clock distribution nodes (106); and a plurality of phase detectors (112), each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes (106), wherein the DDL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes (106) are substantially coincident.</p> |
