| 摘要 |
<p>The invention relates to a method of dual-stage scrambling of addresses (LogAdr) with which a central processor (10) accesses a memory (13). A first encryption logic (11) applies a fixed, unchangeable key (KEY1), whereas a second encryption logic (12) applies a changeable second key (KEY2) stored in the memory (13). The configuration data written during the initialization phase of the central processor (10) are preferably stored in a special configuration range which is accessed via a bypass (15) while bypassing the second encryption logic (12). The bypass is activated by a bypass logic (14) which compares the addresses (Cipher1) encrypted in the first stage with values (SecRowCipher1, SecRowCipher2) stored during the initialization phase.</p> |
