| 摘要 |
The present invention provides a fabricating process for forming multi-layered metal bumps by electroless plating, comprising the steps of: providing an IC chip or a semiconductor substrate on which there are provided a plurality of pads; dispensing a first dielectric layer, exposing the pads, roughing the surface to be redistributed by chemical or physical approaches, activating the surface in order to follow-up electroless plating deposition advantageously, and dispensing a second dielectric layer so as to define a redistribution path; depositing a conductive film on the redistribution path by electroless plating, in which the conductive film allows the positions of the pads to be changed so as to be connected to the external circuit; forming a photoresist pattern, exposing a plurality of pre-determined positions on the conductive film so as to redistribute the positions for the metal bumps formed later; performing activation on the pre-determined positions so as to generate an activator; forming initial metal bumps of a pre-determined thickness on the pads by electroless plating; removing the photoresist pattern, completely exposing the metal bumps; dispensing a third dielectric layer, having a thickness less than the height of the metal bumps and a window more than the size of the metal bumps, so as to expose the metal bumps; and forming a peripheral metal layer covering the periphery of the metal bumps, in which the conductivity and the RF characteristics of the peripheral metal layer are better than those of the metal bumps so as to be electrically connected to the conductive film. |
