| 摘要 |
<p>A semiconductor memory test apparatus capable of easily generating an address to be input into a defect analysis memory for testing during interleave operation of a memory device having a burst function between banks. Each of the registers corresponding to DUT banks holds a line address of the corresponding bank. When a start row address of one of the banks is input to the DUT, a line address of the same bank as the start row address is read out from the register corresponding to the bank and output to a defect analysis memory together with the start row address. Furthermore, during burst operation of the bank, it is possible to output the line address to the defect analysis memory together the same row address as the memory device generated by calculating the start row address for each clock cycle.</p> |
