Semiconductor storage cell used as a planar localized electron device comprises a layer structure with a control electrode for controlling a current flow through the structure, a bit line, and a storage transistor

摘要

Semiconductor storage cell comprises a layer structure (PT) having a dielectric arranged between semiconductor layers and a control electrode (4) for controlling a current flow through the structure; a bit line (BL); and a storage transistor (ST). The layer structure connects the bit line to the gate electrode (2). The cell further comprises a selective transistor (AT) lying in series with the storage transistor with the gate electrode connected to the control electrode of the layer structure and a word line (WL). The selective transistor and the storage transistor are arranged between the bit line and a ground line (GL). An Independent claim is also included for a process for the production of the semiconductor storage cell. Preferred Features: The selective transistor and the layer structure are formed in such a way that the voltage of the selective transistor is less than the voltage of the layer structure.