| 摘要 |
A method of forming an integrated-circuit device (10) which provides increased packing of unrelated conductors such as first gate (14) and second gate (16). Strap (20) electrically connects conductor contact area (28) to moat contact area (30) and yet also overlies and overlaps gate (16) above the overlap area (27) without any danger of shorting first gate (14) to second gate (16). According to the invention, the possibility of shorting strap (20) to second gate (16) and hence first gate (14) to second gate (16), is eliminated in the processing sequence wherein second insulating layer (24) is patterned to expose conductor contact area (28) at a prior step in the processing sequence. Subsequently, a third insulating layer (26) is formed to re-cover conductor contact area (28), yet the thickness of third insulating layer (26) is substantially less than the combination of the thickness of third insulating layer (26) and second insulating layer (24). Hence the etching requirements to re-expose conductor contact area (28), when moat contact area (30) is also exposed, is diminished. Hence the etch to expose conductor contact area (28) and moat contact area (30) does not run the risk of exposing gate (16) at overlap area (27), since the insulation over overlap area (27) is substantially thicker than third insulating layer (26) as noted above. According to the invention, strap (20) is formed to overlie second gate (16) so that second gate (16) may be laterally disposed immediately adjacent moat contact area (30). |
