发明名称 Memory architecture with refresh and sense amplifiers
摘要 <p>An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously. &lt;IMAGE&gt;</p>
申请公布号 EP1258887(A2) 申请公布日期 2002.11.20
申请号 EP20020010358 申请日期 2002.05.07
申请人 INFINEON TECHNOLOGIES AG 发明人 JAIN, RAJ KUMAR
分类号 G11C11/405;G11C11/406;G11C11/4091;H01L21/8242;H01L27/108;H01L27/11;(IPC1-7):G11C8/16 主分类号 G11C11/405
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