发明名称 |
Method and apparatus for data compression and decompression for a data processor system |
摘要 |
During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.
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申请公布号 |
US6484228(B2) |
申请公布日期 |
2002.11.19 |
申请号 |
US20010008074 |
申请日期 |
2001.11.05 |
申请人 |
MOTOROLA, INC. |
发明人 |
BRETERNITZ, JR. MAURICIO;SMITH ROGER A. |
分类号 |
G06F9/318;G06F9/38;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/318 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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