发明名称 Method of forming a highly integrated non-volatile semiconductor memory device
摘要 The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor. The method comprises the steps of: forming a conductive layer on a gate insulating film; forming a dummy layer over the conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask, thereby to form a gate structure removing the resist pattern; forming side wall insulation films on side walls of the gate structure; forming an inter-layer insulator so that the gate structure and the side wall insulation films are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that at least a top portion of the dummy layer is etched; removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that a planarized surface of the inter-layer insulator and the side wall insulation films is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.
申请公布号 US6482697(B1) 申请公布日期 2002.11.19
申请号 US20000705880 申请日期 2000.11.06
申请人 NEC CORPORATION 发明人 SHIRAI HIROKI
分类号 H01L21/8247;H01L21/28;H01L21/336;H01L27/10;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L21/336 主分类号 H01L21/8247
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