发明名称 Method for identifying and correcting error in a central processing unit
摘要 A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions. For proactive debugging, the CPU compares instructions to be executed with each of the known-to-be-erroneous instructions, and on finding a match, injects the corresponding fix instructions into the to-be-executed instructions. Therefore, known errors e.g. the PENTIUM arithmetic bug are avoided, e.g. by replacing one arithmetic instruction with another arithmetic instruction. Moreover, if an error has not yet been debugged, a temporary fix instruction can be used to gracefully terminate an application.
申请公布号 US6484274(B1) 申请公布日期 2002.11.19
申请号 US19990430522 申请日期 1999.10.29
申请人 ADVANCED MICRO DEVICES, INC. 发明人 LEE SHERMAN;KYLE DAVID G.
分类号 G06F11/28;G06F11/22;G06F11/34;G06F11/36;(IPC1-7):H02H3/05 主分类号 G06F11/28
代理机构 代理人
主权项
地址