发明名称
摘要 <p>PROBLEM TO BE SOLVED: To achieve small-sized, lightweight electronic equipment by making a package small in size by outputting data of the high-order bits from a 1st memory and data of the low-order bits from a 2nd memory. SOLUTION: The signal lines of the data bus 100 connected to an MPU 101 are divided into two groups of data buses 100-1 and 100-2, and RAMs 102-1 to 102-k and ROMs 103-1 to 103-k connected to the data bus 100-1 are mounted on a surface A and RAMs 102-(k+1) to 102-N and ROMs 103-(k+1) to 103-N connected to the data bus 100-2 are mounted on a surface A. Namely, the memory module has the 1st memories arranged on one surface of the substrate and the 2nd memories arranged on the other surface of the substrate, and the data of the high-order bits are outputted from the 1st memories and the data of the low-order bits are outputted from the 2nd memories. The data buses need not be connected between the surfaces A and B and the number of via holes is decreased.</p>
申请公布号 JP3345381(B2) 申请公布日期 2002.11.18
申请号 JP19990329217 申请日期 1999.11.19
申请人 发明人
分类号 G06F1/18;G06F12/00;G06F12/06;G06F13/16;H01L25/065;H01L25/07;H01L25/18;(IPC1-7):G06F1/18 主分类号 G06F1/18
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