HIGH-SPEED AD CONVERSION SIGNAL PROCESSING UNIT, RF RECEIVER CIRCUIT, DIGITAL RECEIVER FRONT END CIRCUIT, MRI DEVICE AND HIGH-SPEED ANALOG/DIGITAL CONVERTER

摘要

PURPOSE: To provide a high-speed ad conversion signal processing unit that properly transfers digital data from a high-speed analog/digital converter to a digital signal processing section. CONSTITUTION: A dual clock synchronization type FIFO 34 stores digital data in a timing when a high-speed analog/digital converter 21 outputs digital data D-AD (timing on the basis of a data ready signal DATA-RADY). Then digital data D-FIFO are read from the dual clock synchronization type FIFO 34 in an operating timing of a digital signal processing section 40 (timing on the basis of a digital signal processing clock signal CLK-DIG), and given to the digital signal processing section 40. Thus, even when there exists a timing difference between the timing when the high-speed analog/digital converter outputs digital data and the clock signal for digital signal processing used by the digital signal processing section, it is absorbed and the digital data can properly be given.