| 摘要 |
PURPOSE: A variable delay circuit for reducing an influence of supply voltage and a PLL(Phase Locked Loop) using the same are provided to restrain a variation of delay time by detecting and compensating a variation of supply voltage. CONSTITUTION: A variable delay circuit is formed with an inverter, a plurality of current source transistors(MP0,MN0), and a plurality of diode coupling transistors(MP1,MN1). The inverter is formed with switching transistors or selector transistors(MP2,MN2). The current source transistors(MP0,MN0) are combined between the inverter and supply voltages(VDD,VSS) in order to supply driving current to the inverter. A delay time of the variable delay circuit is controlled by output current of the current source transistors(MP0,MN0). The current source transistors(MP0,MN0) is controlled by bias voltages(VBP,VBN) generated from a bias generator. A voltage(VDS) between both ends of the diode coupling transistor(MP1) is increased if the supply voltage(VDD) is increased. The voltage(VDS) between both ends of the diode coupling transistor(MP1) is increased if the supply voltage(VDD,VSS) is increased.
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