发明名称 Circuit simulation using dynamic partitioning and on-demand evaluation
摘要 An EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation. The circuit simulator includes a static partitioner, a dynamic partitioner and an evaluation scheduler. The static partitioner pre-forms a number of static partitions for the circuit. During simulation, the dynamic partitioner forms and re-forms a number of dynamic partitions referencing the static partitions. At each simulation time step, the evaluation scheduler determines which, if any, of the dynamic partitions have to be evaluated, and evaluating on-demand only those where evaluations are necessary. In one embodiment, when evaluations are performed, they are performed through matrix solution when accuracy is needed.
申请公布号 US6480816(B1) 申请公布日期 2002.11.12
申请号 US19990333124 申请日期 1999.06.14
申请人 DHAR SANJAY 发明人 DHAR SANJAY
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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