Electrostatic discharge (ESD) latch-up protective circuit for an integrated circuit

摘要

The ESD protective circuit proceeds from a modified lateral pnpn "latch-up" protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.