| 摘要 |
A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for counting a number representing a Read Pointer, a second counter for counting a number representing a Write Pointer, a third counter for holding and managing the number of remaining empty entries in the FIFO memory circuit, and comparison means for comparing the value of the third counter with a constant value. Write Ready, Read Ready, Full, Empty, Almost Full and Almost Empty which are status signals of the FIFO memory circuit are produced at a high speed by comparison carried out by the comparison means without using a subtractor.
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