| 摘要 |
To provide equal cell programming conditions, the integrated circuit device has a number of bitline compensation elements each coupled in series with a separate bitline, and a number of wordline compensation elements each coupled in series with a separate wordline. The resistances in these compensation elements are such that a variation in a sum of (1) the resistance along the corresponding bitline of a cell between the first terminal of the cell and a far terminal of the bitline compensation element that is coupled to the corresponding bitline and (2) the resistance along the corresponding wordline of the cell between a second terminal of the cell and a far terminal of the wordline compensation element that is coupled to the corresponding wordline, is minimized across the cells of the array.
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