发明名称 |
Memory system for synchronized and high speed data transfer |
摘要 |
A plurality of memory devices are connected parallel to each other commonly to signal lines extending in one direction, and signals are transmitted in one direction along the signal lines. The sum of the time of signal propagation from a transmission unit to a selected memory device and the time of signal propagation from the selected memory devices to a reception unit is constant for every memory device. Therefore, offset in access times to the memory chips in the memory system can be eliminated.
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申请公布号 |
US6480946(B1) |
申请公布日期 |
2002.11.12 |
申请号 |
US19990283758 |
申请日期 |
1999.04.02 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TOMISHIMA SHIGEKI;ISHIKAWA MASATOSHI;OOISHI TSUKASA |
分类号 |
G06F13/16;G06F12/00;G11C5/06;G11C7/22;G11C11/401;G11C11/407;G11C11/4076;G11C11/409;(IPC1-7):G06F12/00;G06F13/42;G06F1/12;H04L7/00;H04L5/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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