发明名称 Method and apparatus for controlling memory access by a plurality of devices
摘要 When each access apparatus is to update its own data written in a common memory device, the transmitting unit of each access apparatus transmits the previous data previously written in the memory device and new data to be newly written in the memory device as a pair of data via a bus. Upon receiving the pair of data from the access apparatus, a determination unit in the common memory device determines whether the data stored in a memory coincides with the previous data received from the access apparatus. If these two data coincide with each other, the data in the memory is rewritten into the new data; otherwise, a data update in the memory is rejected.
申请公布号 US6480945(B2) 申请公布日期 2002.11.12
申请号 US19990350624 申请日期 1999.07.09
申请人 YAMATAKE CORPORATION 发明人 KUMEDA YASUO
分类号 G06F15/16;G06F9/46;G06F9/52;G06F12/00;G06F15/177;(IPC1-7):G06F12/14;G06F13/14 主分类号 G06F15/16
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