发明名称 Signal processing circuit
摘要 A recording apparatus operates in any one of a standard mode and a high-quality mode. The apparatus records a video signal of a standard format during the standard mode of operation. The apparatus records a video signal of a high-quality format during the high-quality mode of operation. A signal processing circuit for use in the apparatus includes a first device for subjecting a first signal to a nonlinear emphasis process to convert the first signal into a second signal. A second device operates for selecting one of the first signal and the second signal in response to whether the apparatus operates in the standard mode or the high-quality mode, and for outputting the selected signal as a third signal. A third device operates for subjecting the third signal to a nonlinear de-emphasis process to convert the third signal into a fourth signal. A fourth device operates for selecting one of the third signal and the fourth signal in response to whether the apparatus operates in the standard mode or the high-quality mode, and for outputting the selected signal as a fifth signal. A fifth device operates for separating a sync signal from the fifth signal. During the standard mode of operation of the apparatus, the first device selects the first signal, and the fourth device selects the third signal. During the high-quality mode of operation of the apparatus, the first device selects the second signal, and the fourth device selects the fourth signal.
申请公布号 US6480668(B1) 申请公布日期 2002.11.12
申请号 US19990364068 申请日期 1999.07.30
申请人 VICTOR COMPANY OF JAPAN, LTD. 发明人 MUROYA TSUYOSHI;MURAYAMA KOHEI
分类号 H04N5/91;H04N5/922;H04N9/80;H04N9/83;(IPC1-7):H04N5/91 主分类号 H04N5/91
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