发明名称 |
Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)-- |
摘要 |
A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.
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申请公布号 |
US6480937(B1) |
申请公布日期 |
2002.11.12 |
申请号 |
US20010623052 |
申请日期 |
2001.01.09 |
申请人 |
PACT INFORMATIONSTECHNOLOGIE GMBH |
发明人 |
VORBACH MARTIN;MUENCH ROBERT |
分类号 |
G06F12/08;G06F15/78;G06F15/82;H03K19/173;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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