发明名称 |
Multiple voted logic cell testable by a scan chain and system and method of testing the same |
摘要 |
A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.
|
申请公布号 |
US6480019(B2) |
申请公布日期 |
2002.11.12 |
申请号 |
US20010829130 |
申请日期 |
2001.04.09 |
申请人 |
GOODRICH CORPORATION |
发明人 |
WALDIE ARTHUR HOWARD;JAMES ROBERT WARD;CHANG KUO-CHUAN |
分类号 |
G01R31/3185;(IPC1-7):H03K19/00 |
主分类号 |
G01R31/3185 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|