发明名称 |
High speed network switch bus clock |
摘要 |
A high-speed network switch includes a data bus for transmitting data between devices. The data bus includes a plurality of data lines and a clock line. As packet data is received by the high-speed network switch, the packet data is divided into byte-wide cells for transmission over the data lines. While the cells are transmitted over the data lines, a half-speed clock is transmitted over the clock line. Transitions in the half-speed clock occur during transmission of the cell data. The transitions are used by a receiving device to sample the byte-wide cells.
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申请公布号 |
US6480498(B1) |
申请公布日期 |
2002.11.12 |
申请号 |
US19980108874 |
申请日期 |
1998.07.01 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
GAUDET BRIAN;PAGNON VICKIE |
分类号 |
H04J3/06;(IPC1-7):H04L12/46 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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