SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND MEMORY MODULE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can adjust the output data phase and a memory system using the semiconductor memory devices. SOLUTION: The DLL circuit of DDR SDRAM is provided with a replica buffer for flight time compensation 36 in addition to a replica buffer for output buffer delay compensation 34. The phase of clock signal CLKP that is outputted outside locking to the clock signal BUFFCLK can be adjusted responding to the control signal b[1:0]. The timing of data arrival from each semiconductor device can be made even for the controller that receives data together from a plurality of semiconductor devices. The load of controller is reduced, as it is not necessary to take in the data in response to the strobe signal DQS.