| 摘要 |
PROBLEM TO BE SOLVED: To provide the smallest cell area while providing the largest area of a capacitor in a device structure with the use of a local wiring. SOLUTION: In the device structure of the present invention, by metal wiring with the poly-silicon by employing a poly-silicon plug process in an upper electrode forming a ferroelectric memory cell structure and the wiring of an electrode (a source/drain) of a MOS type field effect transistor, a memory cell area is decreased and a storage capacitance is increased as well. In the manufacturing method, a contact pad process of currently used Fig. 2 is made unnecessary and still further deterioration of a ferroelectric material under a reducing atmosphere, which is a weak point of a ferroelectric process, is prevented. In the method for manufacturing the device, in order to protect deterioration of the ferroelectric material, by employing a local wiring material where an oxide film is deposited and then a poly-silicon plug is formed, the poly-silicon plug having low resistance can be formed.
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