| 摘要 |
PROBLEM TO BE SOLVED: To surely transfer trace data for debugging to an external debugger without being late for the data transfer speed of a tracing source even though a bus clock frequency is accelerated and a bus bit width becomes large. SOLUTION: The data of any of a control bus 36, an address bus 37 and a data bus 38 are alternately stored in two trace buffer memories A and B, and data are also alternately outputted from the two trace buffer memories A and B.
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