| 摘要 |
The memory store is organized in words according to an array of rows and columns, and the selection of a word is ensured by the signals for selecting a row and a column (Selrow,Selcol), where the signals are delivered by two address decoders (DECX,DECYm). Each memory-cell word (M0,0) regroups several, in particular 8 for 8-bit word, memory cells (C0,...,C7) on the same row, and each cell comprises a memory transistor of MOS type with a control gate and two channel electrodes the drainn and the source; the control gates of the cells of each row are connected together to a gate control line (CG0), and the drain of each cell is connected to the respective bit line (B10,...,B17). Each word comprises a word-selecting transistor (TS0,0) by the source, and is controlled by the low-voltage selection signals (SelRow,SelCol). The gate control lines (CG0,...Cgm-1) are controlled by a polarization circuit (1) receiving the address selection signals. The gate control lines are regrouped at least two by two, and each group is controlled by a higher-voltage switching circuit of the polarization circuit. The gate control lines put together correspond to the to the neighbouring rows. The higher-voltage switching circuit applies either the higher voltage (Vpp) in the case of the write instruction, or a stationary voltage (Vrepos) applied outside of the write operation. The level of stationary voltage is chosen as equal to the level of polarization voltage in the read mode. Each column of memory store comprises bit lines (B10,...,B17), connected to a write circuit (2) for writing (DATA-IN) and to a read circuit (3) for reading (DATA-OUT). The read circuit (3) comprises a precharge circuit associated with a detection circuit comprising differential amplfiers, and the precharge circuit receives an activation instruction before the start of a cycle or a succession of cycles of the read operations. The precharge circuit brings all bit lines to the same precharge voltage (Vpch). The memory store comprises an isolating circuit (EI) between the bit lines and the read circuit (3), which is activated during the write operations. An integrated circuit comprises the read-only memory store of specified architecture.
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