发明名称 Reducing jitter in mixed-signal integrated circuit devices
摘要 A mixed-signal integrated circuit device (100) such as a digital-to-analog converter comprises signal processing circuitry (120-170) operable to produce an output signal (OUT) in dependence upon a received input signal (D1-Dm). Production of the output signal (OUT) is initiated at a time determined by a timing signal (CLK) and is completed at a time which is delayed by a delay time with respect to said timing signal (CLK). The signal processing circuitry (120-170) comprises at least one delay-contributing portion (120, 130, 150, 160) which makes a contribution to the delay time that is affected by variations in a power supply voltage (VDD) applied to the delay-contributing portion concerned. The integrated circuit device (100) is provided with at least one internal supply voltage regulator (110) for connection when the device is in use to a power source external of the device (100) to receive therefrom an external power source voltage (VDD). The supply voltage regulator (110) derives a regulated internal power supply voltage (VDD(REG)) from the external power source voltage (VDD), and this regulated internal power supply voltage (VDD(REG)) is applied to one of the delay-contributing portions (130, 150, 160). At least one further circuitry portion (140, 170) within the integrated circuit device (100) is powered by a supply voltage (VDD) other than the regulated internal power supply voltage (VDD(REG)).
申请公布号 US2002163456(A1) 申请公布日期 2002.11.07
申请号 US20010987279 申请日期 2001.11.14
申请人 FUJITSU LIMITED 发明人 DEDIC IAN JUSO
分类号 H03M1/66;H03K17/00;H03K19/003;H03M1/08;H03M1/74;(IPC1-7):H03M1/66;H03M1/12 主分类号 H03M1/66
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